Integrated circuit and seed layers

ABSTRACT

Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. The low energy ion implantation allows for the distinct placement of both the diffusion barrier and the seed layer. Structures are formed with a barrier/adhesion layer deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. Such structures include aluminum, copper, gold, and silver metal interconnects.

RELATED APPLICATIONS

[0001] This application is a Divisional of U.S. application Ser. No. 10/117,041, filed Apr. 5, 2002, which is a Divisional of U.S. application Ser. No. 09/484,002, filed Jan. 18, 2000, now U.S. Pat. No. 6,376,370, both of which are incorporated herein by reference.

[0002] This application is related to the following co-pending, commonly assigned applications: U.S. application Ser. No. 09/128,859 filed Aug. 4, 1998, now U.S. Pat. No. 6,284,656, U.S. application Ser. No. 09/488,098, filed Jan. 18, 2000, now U.S. Pat. No. 6,429,120, and U.S. application Ser. No. 09/484,303, filed Jan. 18, 2000, which are hereby incorporated by reference.

FIELD OF THE INVENTION

[0003] The present invention relates generally to integrated circuits. More particularly, it pertains to structures and methods for providing seed layers for integrated circuit metallurgy.

BACKGROUND OF THE INVENTION

[0004] One of the main problems confronting the semiconductor processing industry, in the ULSI age, is that of Capacitive-Resistance loss in the wiring levels. This has led to a large effort to reduce the resistance of and lower the capacitive loading on the wiring levels. Since its beginning, the industry has relied on aluminum and aluminum alloys for wiring. In a like manner, the industry has mainly relied on SiO₂ as the insulator of choice, although polyimide was used in a number of products by one vendor (IBM), for a number of years. The capacitive resistance problem grows with each succeeding generation of technology. As the dimensions decrease the minimum line space combination decreases, thus increasing both capacitance and resistance, if the designer is to take advantage of the improved ground rules.

[0005] To improve the conductivity, it has been suggested by numerous investigators, that copper or perhaps silver or gold metallurgy be substituted for the aluminum metallurgy, now being used. Several potential problems have been encountered in the development of these proposed metallurgies. One of the main ones is the fast diffusion of copper through both silicon and SiO₂. This along with the known junction poising effects of copper and gold have led to proposals to use a liner, to separate these metallurgies from the SiO₂ insulator.

[0006] For example, an article authored by Karen Holloway and Peter M. Fryer, entitled, “Tantalum as a diffusion barrier between copper and silicon”, Appl. Phys. Letter vol. 57, No. 17, 22 Oct. 1990, pp. 1736-1738, suggests the use of a tantalum metal liner. In another article authored by T. Laursen and J. W. Mayer, entitled, “Encapsulation of Copper by Nitridation of Cu—Ti Alloy/Bilayer Structures”, International Conference on Metallurgical Coatings and Thin Films, San Diego, Calif., Apr. 21-25, 1997, Abstract No. H1.03, pg. 309, suggests using a compound such as CuTi as the liner. Still another article published by Vee S. C. Len, R. E. Hurley, N. McCusker, D. W. McNill, B. M. Armstrong and H. S. Gamble, entitled, “An investigation into the performance of diffusion barrier materials against copper diffusion using metal-oxide-semiconductor (MOS) capacitor structures”, Solid-State Electronics 43 (1999) pp. 1045-1049 suggests using a compound such as TaN as the liner. These approaches, however, do not fully resolve the above-stated problem of the minimum line space decreases. Thus, the shrinking line size in the metal line and liner combination again increases both the capacitance and resistance.

[0007] At the same time other investigators, in looking at the capacitive loading effect, have been studying various polymers such as fluorinated polyimides as possible substitutions for SiO₂ insulators. Several of these materials have dielectric constants considerably lower than SiO₂. However as in the case of SiO₂, an incompatibility problem with copper metallurgy has been found. For example, in a presentation by D. J. Godbey, L. J. Buckley, A. P. Purdy and A. W. Snow, entitled, “Copper Diffusion in Organic Polymer Resists and Inter-level Dielectrics”, at the International Conference on Metallurgical Coatings and Thin Films, San Diego, Calif., Apr. 21-25, 1997, Abstract H2.04 pg. 313, it was shown that polyimide, and many other polymers, react with copper during the curing process, forming a conductive oxide CuO₂, which is dispersed within the polymer. This then raises the effective dielectric constant of the polymer and in many cases increases the polymers conductivity. In addition it has been found that reactive ion etching (RIE) of all three metals, copper, silver or gold, is difficult at best.

[0008] Other approaches by investigators have continued to look for ways to continue to use aluminum wiring with a lower dielectric constant insulator. This would decrease the capacitive load with a given inter-line space but require wider or thicker lines. The use of thicker lines would increase the capacitive loading in direct proportion to the thickness increase. Thus to some measure, it defeats the objectives of decreasing the capacitive loading effects. Therefore, the use of thicker lines should be avoided as much as possible. As the resistivity of the line is directly proportional to its cross-sectional area, if it cannot be made thicker, it must be made wider. If however the lines are made wider, fewer wiring channels can be provided in each metal level. To obtain the same number of wiring channels, additional levels of metal must be provided. This increases the chip cost. So if this approach is to be followed, it is imperative that a low cost process sequence be adopted.

[0009] One approach provided by the present inventor in a co-pending application, entitled, “Copper Metallurgy in Integrated Circuits”, filed Aug. 4, 1998, application Ser. No. 09/128,859, proposes a method to solve many of the problems associated with using copper in a polymer insulator. This process, which was specifically designed to be compatible with a polymer or foam insulation, required that the unwanted copper on the surface of each layer be removed by Chemical Mechanical Polishing (CMP) or a similar planarizing process. However, this method may require careful process control, leading to additional expense. Another approach is provided in a co-pending application by Kie Ahn and Leonard Forbes, entitled “Method for Making Copper and Other Metal Interconnections in Integrated Circuits”, filed Feb. 27, 1998, U.S. Ser. No. 09/032,197, which proposes a method using ionized sputtering to form the underlayer, then forming a low wetting layer on the areas where no copper is desired using jet vapor deposition. The copper is deposited with ionized Magnetron sputtering followed by hydrogen annealing. The excess copper is then removed by CMP as in the aforementioned application.

[0010] Another process is described by the present inventor in a co-pending application, entitled, “Integrated Circuit with Oxidation Resistant Polymeric Layer”, filed Sep. 1, 1998, U.S. Ser. No. 09/145,012, which eliminates many of the CMP processes and uses lift-off to define the trench and the seed layer simultaneously. A process is also described by the present inventor in a co-pending application, entitled, “Conductive Structures in Integrated Circuits” filed Mar. 1, 1999, U.S. Ser. No. 09/259,849, which required a CMP process to remove unwanted seed material prior to a selective deposition of the metal layers in a damascene or dual damascene process.

[0011] The use of CMP has proven to be effective in reducing local non-planarity. However, extensive dishing in wide lines and rounding of corners of the insulator are a common occurrence. It has been found that by maintaining a regular structure through the use of dummy structures and small feature sizes, it is possible to planarize a level to a nearly flat surface. The use of these techniques are however costly and in some cases come with density or performance penalties. It is, however, generally possible to planarize a structure prior to the metal levels using these methods with little or no density penalty. The use of electroless plating has been suggested in an article authored by Yosi Schacham-Diamand and Valery M. Dubin, entitled “Copper electroless deposition technology for ultra-large scale-integration (ULSI) metallization”, Microelectronic Engineering 33 (1997) 47-58, however a simple process for obtaining both a barrier layer as well as a seed layer is needed to improve the cost effectiveness of this technique. One technique for seeding polyimide and silicon surfaces using high energy (10-20 Kilo Electron Volts {KEV}) ion implantation has been demonstrated in an article authored by S. Bhansali, D. K. Sood and R. B. Zmood, entitled “Selective electroless copper plating on silicon seeded by copper ion implantation”, Thin Solid Films V253 (1994) pp. 391-394. However this process has not been shown to be implementable into a product structure where a barrier and/or adhesion layer is required.

[0012] For the reasons stated above and for others which will become apparent from reading the following disclosure, structures and methods are needed which alleviate the problems associated with via and metal line fabrication processes. These structures and methods for via and metal line fabrication must be streamlined and accommodate the demand for higher performance in integrated circuits even as the fabrication design rules shrink.

SUMMARY OF THE INVENTION

[0013] The above mentioned problems associated with integrated circuit size and performance, the via and metal line formation process, and other problems are addressed by the present invention and will be understood by reading and studying the following specification. The structures and methods of the present invention include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. According to the teachings of the present invention, the selective deposition of the metal lines avoids the need for multiple chemical mechanical planarization (CMP) steps. The low energy ion implantation of the present invention allows for the distinct placement of both the diffusion barrier and the seed layer. A residual resist can be used to remove the diffusion barrier and the seed layer from unwanted areas on a wafer surface.

[0014] In particular one illustrative embodiment of the present invention includes a method of making a diffusion barrier and a seed layer in an integrated circuit. The method includes patterning an insulator material to define a number of trenches in the insulator layer opening to a number of first level vias in a planarized surface. A barrier/adhesion layer is deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. This novel methodology further accommodates the formation of aluminum, copper, gold, and/or silver metal interconnects.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following detailed description of the preferred embodiments can best be understood when read in conjunction with the following drawings, in which:

[0016]FIG. 1A-1K illustrate one embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention;

[0017]FIG. 2A-2K illustrate another embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention;

[0018]FIG. 3A-3K illustrate another embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention;

[0019]FIG. 4A-4L illustrate another embodiment of the various processing steps for forming vias and metal lines according to the teachings of the present invention;

[0020]FIG. 5 is an illustration of an integrated circuit formed according to the teachings of the present invention.

[0021]FIG. 6 illustrates an embodiment of a system including a portion of an integrated circuit formed according to any of the embodiments described in the present application.

DETAILED DESCRIPTION

[0022] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.

[0023] The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Substrate include doped and unhoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term insulator is defined to include any material that is less electrically conductive than the materials generally referred to as conductors by those skilled in the art. The following detailed description is, therefore, not to be taken in a limiting sense.

[0024] What is disclosed herein is a low cost process to achieve reduced capacitance and resistance loss in wiring levels. The present invention requires only one complete CMP planarizing coupled with the formation of the first level vias, no matter how many levels of metallurgy are used. What are essentially cleanup CMP steps on each metal level are used in one process sequence. This process can be used with an aluminum, copper, silver, gold or any other material which can subsequently be electrolessly plated or deposited by selective CVD or any other selective deposition process. A polyimide, other polymer or foam polymer can be used as an insulator. It can also be used with an oxide or other inorganic insulating structure if the insulating stack is compatible with the metal being used. It can also be used to form air bridge structures as well. The process uses low energy ion implantation to deposit both the adhesion and/or barrier layer along with the seed layer. This is coupled with using the resist layer which defines the damascene trench as the blocking layer to define the implant areas. Low energy implantation allows the placing of distinct layers of both barrier/adhesion and seed layers. The use of the same resist layers to define both the trench and seed layers allows a low cost implementation of the process.

[0025] Embodiment of a Metal Interconnect Using Copper and Polyimide

[0026]FIGS. 1A-1K illustrate a novel methodology for the formation of metal interconnects and/or a wiring structure in an integrated circuit according to the teachings of the present invention. The novel methodology includes the novel formation of a barrier/adhesion layer and a seed layer in an integrated circuit using a low energy ion implantation. The novel methodology also encompasses a novel method of making copper, silver, aluminum, or gold interconnect for an integrated circuit.

[0027]FIG. 1A illustrates a portion of an integrated circuit structure, namely an integrated circuit having a number of semiconductor devices formed in a substrate. FIG. 1 illustrates the structure after a device structure is formed in the substrate and the contact structure to the device structure is in place. One of ordinary skill in the art will understand upon reading this disclosure the manner in which a number of semiconductor structures, e.g. transistors, can be formed in a substrate. One of ordinary skill in the art will also understand upon reading this disclosure the manner in which a contact structure can be formed connecting to a given semiconductor device in a substrate. For example, FIG. 1A illustrates the structure after a number of device structures, e.g. transistor 101A and 101B are formed in the substrate 100. An insulator layer 102 is deposited over the number of semiconductors 101A and 101B. The deposition of the insulator layer 102 can include depositing a layer of Si₃N₄ having a thickness in the range of 100 to 500 Angstroms (Å). This insulator layer will also serve as an additional barrier to impurities coming from subsequent processing steps. Contact holes 105A and 105B are opened to the number of device structures 101A and 101B using a photolithography technique. One of ordinary skill in the are will understand, upon reading this disclosure, the manner in which a photolithography technique can be used to create contact holes 105A and 105B. In one embodiment of the present invention a titanium silicide liner 106A and 106B is placed in the contact holes 105A and 105B, such a through a process such as chemical vapor deposition (CVD). Next, tungsten vias 107A and 107B can be deposited in the contact holes 105A and 105B. The tungsten vias 107A and 107B can be deposited in the contact holes using any suitable technique such as using a CVD process. The excess tungsten is then removed from the wafer surface by chemical mechanical planarization (CMP) or other suitable processes to form a planarized surface 109.

[0028] As shown in FIG. 1B, a first polymer layer 108, or first layer of polyimide 108, is deposited over the wafer surface. The first polymer layer 108 may be deposited using, for example, the process and material described in co-pending and commonly assigned application U.S. Ser. No. 09/128,859, entitled “Copper Metallurgy in Integrated Circuits,” which is hereby incorporated by reference. In one embodiment, depositing a first polymer layer 108 includes depositing a foamed polymer layer 108. In one embodiment, the first layer of polyimide 108 is deposited and cured, forming a 5000 Å thick layer of polymer 108 after curing. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the first layer of polyimide 108, or insulator layer/material 108, may also be deposited as suited for forming a first level metal pattern, the invention is not so limited. The first layer of polyimide 108, or first insulator layer/material 108 is patterned to define a number of trenches 110 in the first insulator layer 108 opening to a number of first level vias, e.g. tungsten vias 107A and 107B in planarized surface 109. In other words, a first level metal pattern 110 is defined in a mask layer of photoresist 112 and then the first layer of polyimide 108 is etched, using any suitable process, e.g. reactive ion etching (RIE), such that the first level metal pattern 110 is defined in the polyimide. According to the teachings of the present invention, a residual photoresist layer 112 is left in place on the first insulator layer 108 in a number of region 113 outside of the number trenches 110. The structure is now as appears in FIG. 1B.

[0029] As shown in FIG. 1C, a first barrier/adhesion layer 114 is deposited in the number of trenches 110 using a low energy ion implantation. In one embodiment according to the teachings of the present invention, depositing the barrier/adhesion layer 114 includes depositing a layer of zirconium 114 having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the barrier/adhesion layer 114 includes depositing a barrier/adhesion layer 114 of titanium and/or hafnium. In one embodiment, depositing the depositing a layer of zirconium 114 includes depositing a layer of zirconium 114 having a thickness of approximately 50 Å. This can be achieved using a 10¹⁷ ion implant of zirconium, i.e. 10¹⁷ ions of zirconium per square centimeter (cm²). According to the teachings of the present invention, the layer of zirconium 114 is implanted at 100 electron volts (eV) into the surface of the trenches 110 in the polymer layer 108 using a varying angle implant (∝), as represented by arrows 111, where the angle of implantation is changed from normal to the wafer surface to 15 degrees off normal. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation is changed from normal to the planarized surface 109 to approximately 15 degrees off normal deposits the barrier/adhesion layer 114 on all surfaces in the number of trenches 110. The structure is now as appears in FIG. 1C.

[0030] In FIG. 1D, a first seed layer 116 is deposited on the first barrier/adhesion layer 114 using a low energy ion implantation. According to the broader teachings of the present invention, depositing the seed layer 116 on the barrier/adhesion layer 114 includes depositing a seed layer 116 selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer 116 includes depositing a layer of copper 116 having a thickness of approximately a 100 Å. This can be achieved using an 8×10¹⁶ ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper 116 at 100 electron volts (eV) into the surface of the trenches 110 in the polymer layer. Also the layer of copper 116 is implanted at an angle normal to the wafer's surface, as shown by arrows 115. As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper 116 at an angle normal to the planarized surface results in the seed layer of copper 116 remaining on a bottom surface 118 in the number of trenches 110 and to a much lesser extent on the side surfaces 117 of the number of trenches 110. In one embodiment, an optional layer of aluminum 121 is deposited over the copper seed layer 116 again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum 121 is deposited to have a thickness of approximately a 50 Å. This can be achieved using a 3×10¹⁶ ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum 121 is used to protect the copper seed layer 116 from oxidation prior to subsequent processing steps. The structure is now as shown in FIG. 1D.

[0031]FIG. 1E illustrates the structure after the next sequence of process steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer 112 has served as a blocking layer to define the implant areas for the barrier/adhesion layer 114, the seed layer 116, and the layer of aluminum 121. The residual photoresist layer 112 is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer 112 includes removing the unwanted aluminum layer 121, the unwanted seed layer 116, and the unwanted barrier/adhesion layer 114 from other areas of the wafer's surface, e.g., from over a number of regions 113 outside of the trenches 110 on a top surface 119 of the first insulator layer 108. The structure is now as shown in FIG. 1E.

[0032] In FIG. 1F, a metallic conductor 120, or number of first level metal lines 120, is deposited over the seed layer 116 in the number of trenches 110. According to teachings of the present invention, metallic conductor 120, or number of first level metal lines 120, is selected from the group consisting of aluminum, copper, silver, and gold depending on the type of seed layer 116 which was deposited. According to this embodiment, the metallic conductor 120, or number of first level metal lines 120 are selectively formed on the copper seed layer 116 such that the number of copper metal lines 120, or first level copper metal lines 120 are not formed on the top surface 119 of the first insulator layer 108. In one embodiment, the metallic conductor 120, or number of first level metal lines 120, is deposited using a selective CVD process. In another embodiment, depositing a metallic conductor 120, or number of first level metal lines 120, over the seed layer 116 includes depositing a metallic conductor 120 using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the number of trenches 110 to the top surface 119 of the first insulator layer 108.

[0033] As shown in FIG. 1G, the process sequence may be continued to form any number of subsequent metal layers in a multilayer wiring structure. FIG. 1G illustrates the structure after the next sequence of processing steps. In FIG. 1G, a dual damascene process is used to define and fill a first to a second level of vias and a second level metallurgy. To do so, a second polymer layer 124, or second layer of polyimide 124, is deposited over the wafer surface, e.g. the metallic conductor 120, or number of first level metal lines 120, and the first polymer layer 108. The second polymer layer 124 may similarly be deposited using, for example, the process and material described in co-pending and commonly assigned application U.S. Ser. No. 09/128,859, entitled “Copper Metallurgy in Integrated Circuits,” which is hereby incorporated by reference. In one embodiment, depositing a second polymer layer 124 includes depositing a foamed second polymer layer 124. In one embodiment, the second polymer layer 124 is deposited and cured, forming a 10,000 Å thick second polymer layer 124 after curing. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the second polymer layer 124, or second insulator layer/material 124, may also be deposited as suited for forming a first to a second level of vias, e.g. second level vias, and a number of second level metal lines, the invention is not so limited. The second polymer layer 124, or second insulator layer/material 124 is patterned to define a second level of vias and a number of second level metal lines in the second insulator layer/material 124 opening to the metallic conductor 120, or number of first level metal lines 120. In other words, a second level of vias is defined in a second mask layer of photoresist 126 and then the second polymer layer 124 is etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of via openings 128 are defined in the polyimide. Using the dual damascene process, a number of second level metal lines are also defined in a second mask layer of photoresist 126 and the second polymer layer 124 is again etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of metal line trenches 130 are defined in the polyimide. One of ordinary skill in the art will understand upon reading this disclosure, the manner in which a photoresist layer 126 can be mask, exposed, and developed using a dual damascene process to pattern a second level of via openings 128 and a second level of metal line trenches 130 in the second insulator layer/material 124.

[0034] As described previously, and according to the teachings of the present invention, a residual photoresist layer 126 is left in place on the second insulator layer/material 124 in a number of regions 132 outside of the second level of metal line trenches 130. A suitable plasma and/or wet cleaning process is used to remove any contaminates from the second level of via openings 128 and a second level of metal line trenches 130, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. The structure is now as appears in FIG. 1G.

[0035]FIG. 1H illustrates the structure 100 after the next sequence of processing steps. In FIG. 1H, a second barrier/adhesion layer 134 is deposited in the second level of via openings 128 and a second level of metal line trenches 130 using a low energy ion implantation. As described above, in one embodiment according to the teachings of the present invention, depositing the second barrier/adhesion layer 134 includes depositing a layer of zirconium 134 having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the second barrier/adhesion layer 134 includes depositing a barrier/adhesion layer 134 of titanium and/or hafnium. In one embodiment, depositing the layer of zirconium 134 includes depositing a layer of zirconium 134 having a thickness of approximately 50 Å. In one embodiment, this is achieved using a 10¹⁷ ion implant of zirconium. According to the teachings of the present invention, the layer of zirconium 134 is implanted at 100 electron volts (eV) into the surface of the second level of via openings 128 and a second level of metal line trenches 130 in the second polymer layer 124 using a varying angle, as shown by arrows 125, implant where the angle of implantation is changed from normal to the wafer surface to 15 degrees off normal. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation is changed from normal to the wafer surface to approximately 15 degrees off normal deposits the barrier/adhesion layer 134 on all surfaces in the second level of via openings 128 and a second level of metal line trenches 130. The structure is now as appears in FIG. 1H.

[0036]FIG. 1I illustrates the structure 100 after the next sequence of processing steps. In FIG. 1I, a second seed layer 136 is deposited on the second barrier/adhesion layer 134 using a low energy ion implantation. According to the broader teachings of the present invention, depositing the second seed layer 136 on the second barrier/adhesion layer 114 includes depositing a second seed layer 136 selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the second seed layer 136 includes depositing a second layer of copper 136 having a thickness of approximately a 100 Å. In one embodiment, this is achieved using an 8×10¹⁶ ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper 136 at 100 electron volts (eV) into the surfaces of the second level of via openings 128 and the polymer layer. Also the layer of copper 136 is implanted at an angle normal to the wafer's surface as shown by arrows 137. As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper 136 at an angle normal to the planarized surface results in the second seed layer of copper 136 remaining on a bottom surface 138 in the second level of via openings 128 and second level of metal line trenches 130 and to a much lesser extent on the side surfaces 140 of the second level of via openings 128 and a second level of metal line trenches 130. In one embodiment, an optional layer of aluminum 141 is deposited over the second copper seed layer 136 again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum is deposited to have a thickness of approximately a 50 Å. In one embodiment, this is achieved using a 3×10¹⁶ ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum 141 is used to protect the second copper seed layer 136 from oxidation prior to subsequent processing steps.

[0037]FIG. 1J illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer 126 has served as a blocking layer to define the implant areas for the second barrier/adhesion layer 134, the second seed layer 136, and the aluminum layer 141. The residual photoresist layer 126 is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer 126 includes removing the unwanted aluminum layer 141, the unwanted seed layer 136, and the unwanted barrier/adhesion layer 134 from other areas of the wafer's surface, e.g. from over a number of regions 132 outside of second level of metal line trenches 130 on a top surface 142 of the second insulator layer 124. The structure is now as shown in FIG. 1J.

[0038] In FIG. 1K, a second metallic conductor 144, or second core conductor 144, is deposited over or formed on the second seed layer 136 and within the second barrier/adhesion layer 134 in the second level of via openings 128 and the second level of metal line trenches 130 in the polymer layer. In this embodiment the second metallic conductor 144, or second core conductor 144, is copper, but in other embodiments of the present invention can be selected from the group consisting of aluminum, silver, and gold. In one embodiment, the second metallic conductor 144, or second core conductor 144, is deposited using a selective CVD process such that the second metallic conductor 144, or second core conductor 144 is not formed on a top surface 142 of the second insulator layer 124. In another embodiment, depositing a second metallic conductor 144, or second core conductor 144, over on the second seed layer 136 and within the second barrier/adhesion layer 134 includes depositing a second metallic conductor 144, or second core conductor 144, using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the second level of via openings 128 and the second level of metal line trenches 130 to the top surface 142 of the second insulator layer 124. Thus, the second barrier/adhesion layer 134, the second seed layer 136, and the second metallic conductor 144, or second core conductor 144, constitute a second number of conductive structures which includes a number of second level vias and a number of second level metal lines which are formed over and connect to a first number of conductive structures, e.g. the first level metal lines 120.

[0039] Embodiment of a Metal Interconnect Using Aluminum Metal Lines and Oxide Insulators

[0040]FIGS. 2A-2K illustrate a novel methodology for the formation of metal interconnects and/or a wiring structure in an integrated circuit according to the teachings of the present invention. The novel methodology includes the novel formation of a barrier/adhesion layer and a seed layer in an integrated circuit using a low energy ion implantation. The novel methodology also encompasses a novel method of making copper, silver, aluminum, or gold interconnect for an integrated circuit.

[0041]FIG. 2A illustrates a portion of an integrated circuit structure, namely an integrated circuit having a number of semiconductor devices formed in a substrate as described above in connection with FIG. 1A. That is, FIG. 2A illustrates the structure after a device structure is formed in the substrate and the contact structure to the device structure is in place. Like FIG. 1A, FIG. 2A illustrates the structure after a number of device structures, e.g. transistor 201A and 201B are formed in the substrate 200. An insulator layer 202 is deposited over the number of semiconductors 201A and 201B. The deposition of the insulator layer 202 can include depositing a layer of Si₃N₄ having a thickness in the range of 100 to 500 Angstroms (Å). This insulator layer will also serve as an additional barrier to impurities coming from subsequent processing steps. Contact holes 205A and 205B are opened to the number of device structures 201A and 201B using a photolithography technique. One of ordinary skill in the are will understand, upon reading this disclosure, the manner in which a photolithography technique can be used to create contact holes 205A and 205B. In one embodiment of the present invention a titanium silicide liner 206A and 206B is placed in the contact holes 205A and 205B, such a through a process such as chemical vapor deposition (CVD). Next, tungsten vias 207A and 207B can be deposited in the contact holes 205A and 205B. The tungsten vias 207A and 207B can be deposited in the contact holes using any suitable technique such as using a CVD process. The excess tungsten is then removed from the wafer surface by chemical mechanical planarization (CMP) or other suitable processes to form a planarized surface 209.

[0042] As shown in FIG. 2B, a first oxide layer 208, e.g. a silicon dioxide layer (SiO₂), is deposited over the wafer surface. In one embodiment, depositing a first oxide layer 208 includes depositing a fluorinated silicon oxide layer 208. The first oxide layer 208 may be deposited using any suitable technique, such as, for example, using a CVD process. In one embodiment, depositing a first oxide layer 208 having a thickness of approximately 5000 Å. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thicknesses for the first oxide layer 208 may also be deposited as suited for forming a first level metal pattern, the invention is not so limited. The first oxide layer 208 is patterned to define a number of trenches 210 in the first oxide layer 208 opening to a number of first level vias, e.g. tungsten vias 207A and 207B in planarized surface 209. In other words, a first level metal pattern 210 is defined in a mask layer of photoresist 212 and then the first oxide layer 208 is etched, using any suitable process, e.g. reactive ion etching (RIE), such that the first level metal pattern 210 is defined in the first oxide layer 208. One of ordinary skill in the art will understand upon reading this disclosure that any desired first level metal pattern 210 can be created using a photolithography technique. According to the teachings of the present invention, a residual photoresist layer 212 is left in place on the first oxide layer 208 in a number of region 213 outside of the number trenches 210. The structure is now as appears in FIG. 2B.

[0043] As shown in FIG. 2C, a first barrier/adhesion layer 214 is deposited in the number of trenches 210 using a low energy ion implantation. In one embodiment according to the teachings of the present invention, depositing the barrier/adhesion layer 214 includes depositing a layer of zirconium 214 having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the barrier/adhesion layer 214 includes depositing a barrier/adhesion layer 214 of titanium and/or hafnium. In one embodiment, depositing the depositing a layer of zirconium 214 includes depositing a layer of zirconium 214 having a thickness of approximately 50 Å. This can be achieved using a 10¹⁷ ion implant of zirconium. According to the teachings of the present invention, the layer of zirconium 214 is implanted at 100 electron volts (eV) into the surface of the trenches 210 in the first oxide layer 208 using a varying angle implant (∝), as represented by arrows 211, where the angle of implantation is changed from normal to the wafer surface to 15 degrees off normal. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation (∝) is changed from normal to the wafer's surface to approximately 15 degrees off normal deposits the barrier/adhesion layer 214 on all surfaces in the number of trenches 210. The structure is now as appears in FIG. 2C.

[0044] In FIG. 2D, a first seed layer 216 is deposited on the first barrier/adhesion layer 214 using a low energy ion implantation. According to the broader teachings of the present invention, depositing the seed layer 216 on the barrier/adhesion layer 214 includes depositing a first seed layer 216 selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer 216 includes depositing a layer of an aluminum copper alloy 216 having a thickness of approximately 110 Å. This can be achieved by depositing a first layer of aluminum 281 on the barrier/adhesion layer 214 to a thickness of approximately 50 Å using a low energy ion implantation of approximately 100 electron volts (eV). A layer of copper 282 is then deposited on the first layer of aluminum 281 to a thickness of approximately 10 Å using a low energy ion implantation of approximately 100 eV. A second layer of aluminum 283 is then deposited on the layer of copper 282 to a thickness of approximately 50 Å using a low energy ion implantation of approximately 100 eV. Also the first seed layer 216 is implanted at an angle normal to the planarized surface, as shown by arrows 215. As one of ordinary skill in the art will understand upon reading this disclosure, implanting the first seed layer 216 at an angle normal to the planarized surface results in the first seed layer 216 remaining on a bottom surface 218 in the number of trenches 210 and to a much lesser extent on the side surfaces 217 of the number of trenches 210.

[0045]FIG. 2E illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer 212 has served as a blocking layer to define the implant areas for the barrier/adhesion layer 214 and the seed layer 216. The residual photoresist layer 212 is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer 212 includes removing the unwanted seed layer 216 and the unwanted barrier/adhesion layer 214 from other areas of the wafer's surface, e.g. from over a number of regions 213 outside of the trenches 210 on a top surface 219 of the first insulator layer 208. The structure is now as shown in FIG. 2E.

[0046] In FIG. 2F, a metallic conductor 220, or number of first level metal lines 220, is deposited over the first seed layer 216 and within the first barrier/adhesion layer 214 in the number of trenches 210. In this embodiment, the metallic conductor 220, or number of first level metal lines 220, is aluminum, but in other embodiments of the present invention the metallic conductor 220, or number of first level metal lines 220, is selected from the group consisting of copper, silver, and gold depending on the type of seed layer 216 which was deposited. In one embodiment, the metallic conductor 220, or number of first level metal lines 220, is deposited using a selective CVD process. In another embodiment, depositing a metallic conductor 220, or number of first level metal lines 220, over the seed layer 216 includes depositing a metallic conductor 220 using electroless plating. According to the teachings of the present invention the number of first level aluminum metal lines 220, is deposited to fill the number of trenches 210 to the top surface 219 of the first oxide layer 208. Thus, the first level aluminum metal lines 220, the first seed layer 216, and the first barrier/adhesion layer 214 in the number of trenches 210 constitute a first number of conductive structures. The copper composition of the first seed layer 216 can be adjusted to give the appropriate percentage of copper in the completed first number of conductive structures. For example, in the above described embodiment the layer thicknesses of the aluminum copper sandwich was designed to give a 0.7 weight percent of copper in the first number of conductive structures.

[0047] As shown in FIG. 2G, the process sequence may be continued to form any number of subsequent metal layers in a multilayer wiring structure. FIG. 2G illustrates the structure after the next sequence of processing steps. In FIG. 2G, a dual damascene process is used to define and fill a first to a second level of vias and a second level metallurgy. To do so, a second oxide layer 224 is deposited over the wafer surface, e.g. the metallic conductor 220, or number of first level metal lines 220, and the first oxide layer 208. In one embodiment, depositing a second oxide layer 224 includes depositing a second fluorinated silicon oxide layer 224. In one embodiment, the second oxide layer 224 is formed to have a thickness of approximately 10,000 Å. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the second oxide layer 224 may also be deposited as suited for forming a first to a second level of vias, e.g. second level vias, and a number of second level metal lines, the invention is not so limited. The second oxide layer 224 is patterned to define a second level of vias and a number of second level metal lines in the second oxide layer 224 opening to the metallic conductor 220, or number of first level metal lines 220. In other words, a second level of vias is defined in a second mask layer of photoresist 226 and then the second oxide layer 224 is etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of via openings 228 are defined in the polyimide. Using the dual damascene process, a number of second level metal lines are also defined in a second mask layer of photoresist 226 and the second oxide layer 224 is again etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of metal line trenches 230 are defined in the second oxide layer 224. One of ordinary skill in the art will understand upon reading this disclosure, the manner in which a photoresist layer 226 can be mask, exposed, and developed using a dual damascene process to pattern a second level of via openings 228 and a second level of metal line trenches 230 in the second oxide layer 224.

[0048] As described previously, and according to the teachings of the present invention, a residual photoresist layer 226 is left in place on the second oxide layer 224 in a number of regions 232 outside of the second level of metal line trenches 230. A suitable plasma and/or wet cleaning process is used to remove any contaminates from the second level of via openings 228 and a second level of metal line trenches 230, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. The structure is now as appears in FIG. 2G.

[0049]FIG. 2H illustrates the structure after the next sequence of processing steps. In FIG. 2H, a second barrier/adhesion layer 234 is deposited in the second level of via openings 228 and a second level of metal line trenches 230 using a low energy ion implantation. As described above, in one embodiment according to the teachings of the present invention, depositing the second barrier/adhesion layer 234 includes depositing a layer of zirconium 234 having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the second barrier/adhesion layer 234 includes depositing a barrier/adhesion layer 234 of titanium and/or hafnium. In one embodiment, depositing the layer of zirconium 234 includes depositing a layer of zirconium 234 having a thickness of approximately 50 Å. In one embodiment, this is achieved using a 10¹⁷ ion implant of zirconium (that is 10¹⁷ ions per square centimeter). According to the teachings of the present invention, the layer of zirconium 234 is implanted at 100 electron volts (eV) into the surface of the second level of via openings 228 and a second level of metal line trenches 230 in the second polymer layer 224 using a varying angle implant (∝), as shown by arrows 225 where the angle of implantation is changed from normal to the wafer surface to 15 degrees off normal. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation, ∝, is changed from normal to the wafer surface to approximately 15 degrees off normal deposits the barrier/adhesion layer 234 on all surfaces in the second level of via openings 228 and a second level of metal line trenches 230. The structure is now as appears in FIG. 2H.

[0050]FIG. 2I illustrates the structure after the next sequence of processing steps. In FIG. 2I, a second seed layer 236 is deposited on the second barrier/adhesion layer 234 using a low energy ion implantation. According to the broader teachings of the present invention, depositing the second seed layer 236 on the second barrier/adhesion layer 214 includes depositing a second seed layer 236 selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer 216 includes depositing a layer of an aluminum copper alloy 216 having a thickness of approximately 110 Å. This can be achieved by depositing a first layer of aluminum 284 on the barrier/adhesion layer 214 to a thickness of approximately 50 Å using a low energy ion implantation of approximately 100 electron volts (eV). A layer of copper 285 is then deposited on the first layer of aluminum 284 to a thickness of approximately 10 Å using a low energy ion implantation of approximately 100 eV. A second layer of aluminum 286 is then deposited on the layer of copper 285 to a thickness of approximately 50 Å using a low energy ion implantation of approximately 100 eV. Also the first seed layer 216 is implanted at an angle normal to the wafer's surface as shown by arrows 237. As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper 236 at an angle normal to the planarized surface results in the second seed layer of copper 236 remaining on a bottom surface 238 in the second level of via openings 228 and to a much lesser extent on the side surfaces 240 of the second level of via openings 228 and a second level of metal line trenches 230.

[0051]FIG. 2J illustrates the structure following the next sequence of process steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer 226 has served as a blocking layer to define the implant areas for the second barrier/adhesion layer 234 and the second seed layer 236. The residual photoresist layer 226 is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer 226 includes removing the unwanted barrier/adhesion layer 234 and the unwanted second seed layer 236, from other areas of the wafer's surface, e.g. from over a number of regions 232 outside of second level of metal line trenches 230 on a top surface 242 of the second oxide layer 224. The structure is now as shown in FIG. 2J.

[0052] In FIG. 2K, a second metallic conductor 244, or second core conductor 244, is deposited over or formed on the second seed layer 236 and within the second barrier/adhesion layer 234 in the second level of via openings 228 and the second level of metal line trenches 230 in the polymer layer. In this embodiment the second metallic conductor 244, or second core conductor 244, is aluminum, but in other embodiments of the present invention the second metallic conductor 244, or second core conductor 244, can be selected from the group consisting of copper, silver, and gold. In one embodiment, the second metallic conductor 244, or second core conductor 244, is deposited using a selective CVD process. In another embodiment, depositing a second metallic conductor 244, or second core conductor 244, over on the second seed layer 236 and within the second barrier/adhesion layer 234 includes depositing a second metallic conductor 244, or second core conductor 244, using electroless plating. The second aluminum conductor 244, or second core conductor 244 is deposited to fill the second level of via openings 228 and the second level of metal line trenches 230 to the top surface 242 of the second insulator layer 224. Thus, the second barrier/adhesion layer 234, the second seed layer 236, and the second metallic conductor 244, or second core conductor 244, constitute a second number of conductive structures which includes a number of second level vias and a number of second level metal lines which are formed over and connect to a first number of conductive structures, e.g. the first level of vias 207A and 207B.

[0053] Embodiment of a Metal Interconnect Using Copper Metal Lines and Oxide Insulators

[0054]FIGS. 3A-3K illustrate a novel methodology for the formation of metal interconnects and/or a wiring structure in an integrated circuit according to the teachings of the present invention. The novel methodology includes the novel formation of a barrier/adhesion layer and a seed layer in an integrated circuit using a low energy ion implantation. The novel methodology also encompasses a novel method of making copper, silver, aluminum, or gold interconnect for an integrated circuit.

[0055]FIG. 3A illustrates a portion of an integrated circuit structure, namely an integrated circuit having a number of semiconductor devices formed in a substrate. FIG. 3 illustrates the structure after a device structure is formed in the substrate and the contact structure to the device structure is in place. One of ordinary skill in the art will understand upon reading this disclosure the manner in which a number of semiconductor structures, e.g. transistors, can be formed in a substrate. One of ordinary skill in the art will also understand upon reading this disclosure the manner in which a contact structure can be formed connecting to a given semiconductor device in a substrate, such as explained in connection with FIG. 1A. For example, FIG. 3A illustrates the structure after a number of device structures, e.g. transistor 301A and 301B are formed in the substrate 300. An insulator layer 302 is deposited over the number of semiconductors 301A and 301B. The deposition of the insulator layer 302 can include depositing a layer of Si₃N₄ having a thickness in the range of 100 to 500 Angstroms (Å). This insulator layer will also serve as an additional barrier to impurities coming from subsequent processing steps. Contact holes 305A and 305B are opened to the number of device structures 301A and 301B using a photolithography technique. One of ordinary skill in the are will understand, upon reading this disclosure, the manner in which a photolithography technique can be used to create contact holes 305A and 305B. In one embodiment of the present invention a titanium silicide liner 306A and 306B is placed in the contact holes 305A and 305B, such a through a process such as chemical vapor deposition (CVD). Next, tungsten vias 306A and 306B can be deposited in the contact holes 305A and 305B. The tungsten vias 307A and 307B can be deposited in the contact holes using any suitable technique such as using a CVD process. The excess tungsten is then removed from the wafer surface by chemical mechanical planarization (CMP) or other suitable processes to form a planarized surface 309.

[0056] As shown in FIG. 3B, a first polymer layer 308, or first layer of polyimide 308, is deposited over the wafer surface. The first oxide layer 308 may be deposited using any suitable technique such as, for example, a CVD process. In one embodiment, depositing a first oxide layer 308 includes depositing a fluorinated silicon oxide layer 308. In one embodiment, the first oxide layer 308 is deposited to have a thickness of approximately 5000 Å. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the first oxide layer 308 may also be deposited as suited for forming a first level metal pattern, the invention is not so limited. The first oxide layer 308 is patterned to define a number of trenches 310 in the first oxide layer 308 opening to a number of first level vias, e.g. tungsten vias 307A and 307B in planarized surface 309. In other words, a first level metal pattern 310 is defined in a mask layer of photoresist 312 and then the first oxide layer 308 is etched, using any suitable process, e.g. reactive ion etching (RIE), such that the first level metal pattern 310 is defined in the first oxide layer 308. According to the teachings of the present invention, a residual photoresist layer 312 is left in place on the first oxide layer 308 in a number of region 313 outside of the number trenches 310. The structure is now as appears in FIG. 3B.

[0057] As shown in FIG. 3C, a first barrier/adhesion layer 314 is deposited in the number of trenches 310 using a low energy ion implantation. In one embodiment according to the teachings of the present invention, depositing the barrier/adhesion layer 314 includes depositing a tantalum nitride layer 314 having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the barrier/adhesion layer 314 includes depositing a barrier/adhesion layer 314 of tantalum and/or CuTi. In one embodiment, depositing the tantalum nitride layer 314 includes first depositing a layer of tantalum 381 to have a thickness of approximately 100 Å using a low energy ion implantation of approximately 100 electron volts (eV) at a varying angle implant (∝), e.g. the angle of implantation (∝) is changed from normal to the planarized surface 309 to approximately 15 degrees off normal as shown by arrows 311. In one embodiment, this is achieved using a 10¹⁷ ion implant of tantalum. Next, according to the teachings of the present invention, a layer of nitrogen 382 is implanted at 700 electron volts (eV) into the layer of tantalum 381. In one embodiment, this is achieved using an 8×10¹⁶ ion implant of nitrogen. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant, where an angle of implantation is changed from normal to the planarized surface 309 to approximately 15 degrees off normal deposits the barrier/adhesion layer 314 on all surfaces in the number of trenches 310. The structure is now as appears in FIG. 3C.

[0058] In FIG. 3D, a first seed layer 316 is deposited on the first barrier/adhesion layer 314 using a low energy ion implantation. According to the broader teachings of the present invention, depositing the seed layer 316 on the barrier/adhesion layer 314 includes depositing a seed layer 316 selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer 316 includes depositing a layer of copper 316 having a thickness of approximately 50 Å. This can be achieved using an 8×10¹⁶ ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper 316 at 100 electron volts (eV) into the first barrier/adhesion layer 314. Also the layer of copper 316 is implanted at an angle normal to the planarized surface 309 as shown by arrows 315. As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper 316 at an angle normal to the planarized surface results in the seed layer of copper 316 remaining on a bottom surface 318 in the number of trenches 310 and to a much lesser extent on the side surfaces 320 of the number of trenches 310. In one embodiment, an optional layer of aluminum 321 is deposited over the copper seed layer 316 again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum 321 is deposited to have a thickness of approximately a 50 Å. This can be achieved using a 3×10¹⁶ ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum 321 is used to protect the copper seed layer 316 from oxidation prior to subsequent processing steps. The structure is now as appears in FIG. 3D.

[0059]FIG. 3E illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer 312 has served as a blocking layer to define the implant areas for the barrier/adhesion layer 314, the seed layer 316, and the layer of aluminum 321. The residual photoresist layer 312 is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer 312 includes removing the unwanted aluminum layer 321, the unwanted seed layer 316, and the unwanted barrier/adhesion layer 314 from other areas of the wafer's surface, e.g. from over a number of regions outside of the trenches 310 on a top surface 319 of the first insulator layer 308. The structure is now as shown in FIG. 3E.

[0060] In FIG. 3F, a metallic conductor 320, or number of first level metal lines 320, is deposited over the seed layer 316 in the number of trenches 310. According to teachings of the present embodiment, the metallic conductor 320, or number of first level metal lines 320, is copper. In one embodiment, the metallic conductor 320, or number of first level metal lines 320, is deposited using a selective CVD process. In another embodiment, depositing a metallic conductor 320, or number of first level metal lines 320, over the seed layer 316 includes depositing a metallic conductor 320 using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the number of trenches 310 to a level approximately 100 Å below the top surface 319 of the first oxide layer 308. At this point, a second layer of tantalum nitride 323 is deposited to a thickness of approximately 100 Å on the copper metallic conductor 320, or number of first level copper lines 320. A chemical mechanical planarization (CMP) cleanup process is then used to remove the tantalum nitride from the top surface 319 of the first oxide layer 308.

[0061] As shown in FIG. 3G, the process sequence may be continued to form any number of subsequent metal layers in a multilayer wiring structure. FIG. 3G illustrates the structure after the next sequence of processing steps. In FIG. 3G, a dual damascene process is used to define and fill a first to a second level of vias and a second level metallurgy. To do so, a second oxide layer 324 is deposited over the wafer surface, e.g. the metallic conductor 320, or number of first level metal lines 320, and the first oxide layer 308. The second oxide layer 324 is again deposited using any suitable technique. In one embodiment, depositing a second oxide layer 324 includes depositing a fluorinated silicon oxide layer 324. In one embodiment, the second oxide layer 324 is deposited to have a thickness of approximately 10,000 Å. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the second oxide layer 324 may also be deposited as suited for forming a first to a second level of vias, e.g. second level vias, and a number of second level metal lines, the invention is not so limited. The second oxide layer 324 is patterned to define a second level of vias and a number of second level metal lines in the second oxide layer 324 opening to the metallic conductor 320, or number of first level metal lines 320. In other words, a second level of vias is defined in a second mask layer of photoresist 326 and then the second oxide layer 324 is etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of via openings 328 are defined in the second oxide layer 324. Using the dual damascene process, a number of second level metal lines are also defined in a second mask layer of photoresist 326 and the second oxide layer 324 is again etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of metal line trenches 330 are defined in the oxide. One of ordinary skill in the art will understand upon reading this disclosure, the manner in which a photoresist layer 326 can be mask, exposed, and developed using a dual damascene process to pattern a second level of via openings 328 and a second level of metal line trenches 330 in the second oxide layer 324.

[0062] As described previously, and according to the teachings of the present invention, a residual photoresist layer 326 is left in place on the second oxide layer 324 in a number of regions 332 outside of the second level of metal line trenches 330. A suitable plasma and/or wet cleaning process is used to remove any contaminates from the second level of via openings 328 and a second level of metal line trenches 330, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. The structure is now as appears in FIG. 3G.

[0063]FIG. 3H illustrates the structure after the next sequence of processing steps. In FIG. 3H, a second barrier/adhesion layer 334 is deposited in the second level of via openings 328 and a second level of metal line trenches 330 using a low energy ion implantation. As described above, in one embodiment according to the teachings of the present invention, depositing the second barrier/adhesion layer 334 includes depositing a tantalum nitride layer 334 having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the second barrier/adhesion layer 334 includes depositing a second barrier/adhesion layer 334 of tantalum and/or CuTi. In one embodiment, depositing the tantalum nitride layer 334 includes first depositing a layer of tantalum 383 to have a thickness of approximately 100 Å using a low energy ion implantation of approximately 100 electron volts (eV) at a varying angle implant (∝), e.g. the angle of implantation (∝) is changed from normal to the wafer's surface to approximately 15 degrees off normal as shown by arrows 325. In one embodiment, this is achieved using a 10¹⁷ ion implant of tantalum. Next, according to the teachings of the present invention, a layer of nitrogen 384 is implanted at 700 electron volts (eV) into the layer of tantalum 383. In one embodiment, this is achieved using an 8×10¹⁶ ion implant of nitrogen. As one of ordinary skill in the art will understand upon reading this disclosure, using a varying angle implant (∝), where an angle of implantation is changed from normal to the wafer's surface to approximately 15 degrees off normal deposits the second barrier/adhesion layer 334 on all surfaces in the second level of via openings 328 and in the second level of metal line trenches 330 formed in the second oxide layer 324. The structure is now as appears in FIG. 3H.

[0064]FIG. 3I illustrates the structure after the next sequence of processing steps. In FIG. 3I, a second seed layer 336 is deposited on the second barrier/adhesion layer 334 using a low energy ion implantation. According to the broader teachings of the present invention, depositing the second seed layer 336 on the second barrier/adhesion layer 314 includes depositing a second seed layer 336 selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the second seed layer 336 includes depositing a second layer of copper 336 having a thickness of approximately 50 Å. In one embodiment, this is achieved using an 8×10¹⁶ ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper 336 at 100 electron volts (eV) into the surfaces of the second level of via openings 328 and the second level of metal line trenches 330 in the polymer layer. Also the layer of copper 336 is implanted at an angle normal to the wafer's surface as shown by arrows 337. As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper 336 at an angle normal to the wafer's surface results in the second seed layer of copper 336 remaining on a bottom surface 338 in the second level of via openings 328 and to a much lesser extent on the side surfaces 340 of the second level of via openings 328 and a second level of metal line trenches 330. In one embodiment, an optional layer of aluminum 341 is deposited over the second copper seed layer 336 again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum is deposited to have a thickness of approximately a 50 Å. In one embodiment, this is achieved using a 3×10¹⁶ ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum 341 is used to protect the second copper seed layer 336 from oxidation prior to subsequent processing steps. The structure is now as shown in FIG. 3I.

[0065]FIG. 3J illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer 326 has served as a blocking layer to define the implant areas for the second barrier/adhesion layer 334, the second seed layer 336, and the aluminum layer 341. The residual photoresist layer 326 is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer 326 includes removing the unwanted aluminum layer 341, the unwanted seed layer 336, and the unwanted barrier/adhesion layer 334 from other areas of the wafer's surface, e.g. from over a number of regions 332 outside of second level of metal line trenches 330 on a top surface 342 of the second insulator layer 324. The structure is now as shown in FIG. 3J.

[0066] In FIG. 3K, a second metallic conductor 344, or second core conductor 344, is deposited over or formed on the second seed layer 336 and within the second barrier/adhesion layer 334 in the second level of via openings 328 and the second level of metal line trenches 330 in the polymer layer. In this embodiment the second metallic conductor 344, or second core conductor 344, is copper, but in other embodiments of the present invention the second metallic conductor 344, or second core conductor 344, can be selected from the group consisting of aluminum, silver, and gold. In one embodiment, the second metallic conductor 344, or second core conductor 344, is deposited using a selective CVD process. In another embodiment, depositing a second metallic conductor 344, or second core conductor 344, over on the second seed layer 336 and within the second barrier/adhesion layer 334 includes depositing a second metallic conductor 344, or second core conductor 344, using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the second level of via openings 328 and the second level of metal line trenches 330 to level approximately 100 Å below the top surface 342 of the second insulator layer 324. At this point, a second layer of tantalum nitride 346 is deposited to a thickness of approximately 100 Å on the second metallic conductor 344, or second core conductor 344. A chemical mechanical planarization (CMP) cleanup process is then used to remove the tantalum nitride from the top surface 342 of the second insulator layer 324. Thus, the second barrier/adhesion layer 334, the second seed layer 336, and the second metallic conductor 344, or second core conductor 344, constitute a second number of conductive structures which includes a number of second level vias and a number of second level metal lines which are formed over and connect to a first number of conductive structures, e.g. the metallic conductor 320, or number of first level metal lines 320.

[0067] Another Embodiment of a Metal Interconnect Using Copper

[0068]FIGS. 4A-4L illustrate a novel methodology for the formation of metal interconnects and/or a wiring structure in an integrated circuit according to the teachings of the present invention. The novel methodology includes the novel formation of a barrier/adhesion layer and a seed layer in an integrated circuit using a low energy ion implantation. The novel methodology also encompasses a novel method of making copper, silver, aluminum, or gold interconnect for an integrated circuit.

[0069]FIG. 4A illustrates a portion of an integrated circuit structure, namely an integrated circuit having a number of semiconductor devices formed in a substrate. FIG. 4A illustrates the structure after a device structure is formed in the substrate and the contact structure to the device structure is in place. One of ordinary skill in the art will understand upon reading this disclosure the manner in which a number of semiconductor structures, e.g. transistors, can be formed in a substrate. One of ordinary skill in the art will also understand upon reading this disclosure the manner in which a contact structure can be formed connecting to a given semiconductor device in a substrate, such as described in connection with FIG. 1A. For example, FIG. 4A illustrates the structure after a number of device structures, e.g. transistor 401A and 401B are formed in the substrate 400. An insulator layer 402 is deposited over the number of semiconductors 401A and 401B. The deposition of the insulator layer 402 can include depositing a layer of Si₃N₄ having a thickness in the range of 100 to 500 Angstroms (Å). This insulator layer will also serve as an additional barrier to impurities coming from subsequent processing steps. Contact holes 405A and 405B are opened to the number of device structures 401A and 401B using a photolithography technique. One of ordinary skill in the are will understand, upon reading this disclosure, the manner in which a photolithography technique can be used to create contact holes 405A and 405B. In one embodiment of the present invention a titanium silicide liner 406A and 406B is placed in the contact holes 405A and 405B, such a through a process such as chemical vapor deposition (CVD). Next, tungsten vias 407A and 407B can be deposited in the contact holes 405A and 405B. The tungsten vias 407A and 407B can be deposited in the contact holes using any suitable technique such as using a CVD process. The excess tungsten is then removed from the wafer surface by chemical mechanical planarization (CMP) or other suitable processes to form a planarized surface 409.

[0070] As shown in FIG. 4B, a first polymer layer 408, or first layer of polyimide 408, is deposited over the wafer surface. The first polymer layer 408 may be deposited using, for example, the process and material described in co-pending and commonly assigned application U.S. Ser. No. 09/128,859, entitled “Copper Metallurgy in Integrated Circuits,” which is hereby incorporated by reference. In one embodiment, depositing a first polymer layer 408 includes depositing a foamed polymer layer 408. In one embodiment, the first layer of polyimide 408 is deposited and cured, forming a 5000 Å thick layer of polymer 408 after curing. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the first layer of polyimide 408, or insulator layer/material 408, may also be deposited as suited for forming a first level metal pattern, the invention is not so limited. The first layer of polyimide 408, or first insulator layer/material 408 is patterned to define a number of trenches 410 in the first insulator layer 408 opening to a number of first level vias, e.g. tungsten vias 407A and 407B in planarized surface 409. In other words, a first level metal pattern 410 is defined in a mask layer of photoresist 412 and then the first layer of polyimide 408 is etched, using any suitable process, e.g. reactive ion etching (RIE), such that the first level metal pattern 410 is defined in the polyimide. According to the teachings of the present invention, a residual photoresist layer 412 is left in place on the first insulator layer 408 in a number of region 413 outside of the number trenches 410. The structure is now as appears in FIG. 4B.

[0071] As shown in FIG. 4C, a first barrier/adhesion layer 414 is deposited in the number of trenches 410 using a low energy ion implantation. In one embodiment according to the teachings of the present invention, depositing the barrier/adhesion layer 414 includes depositing a layer of zirconium 414 having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the barrier/adhesion layer 414 includes depositing a barrier/adhesion layer 414 of titanium and/or hafnium. In one embodiment, depositing the depositing a layer of zirconium 414 includes depositing a layer of zirconium 414 having a thickness of approximately 15 Å. This can be achieved using a 10¹⁷ ion implant of zirconium. According to the teachings of the present invention, the layer of zirconium 414 is implanted at 100 electron volts (eV) into the surface of the trenches 410 in the polymer layer 408 using an angle of implant normal to the wafer's surface as shown by arrows 411. The structure is now as appears in FIG. 4C.

[0072] In FIG. 4D, a first seed layer 416 is deposited on the first barrier/adhesion layer 414 using a low energy ion implantation. According to the broader teachings of the present invention, depositing the seed layer 416 on the barrier/adhesion layer 414 includes depositing a seed layer 416 selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the seed layer 416 includes depositing a layer of copper 416 having a thickness of approximately a 50 Å. This can be achieved using an 8×10¹⁶ ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper 416 at 100 electron volts (eV) into the surface of the trenches 410 in the polymer layer. Also the layer of copper 416 is implanted at an angle normal to the wafer's surface as shown by arrows 415. As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper 416 at an angle normal to the wafer's surface results in the seed layer of copper 416 remaining on a bottom surface 418 in the number of trenches 410 and to a much lesser extent on the side surfaces 420 of the number of trenches 410. In one embodiment, an optional layer of aluminum 421 is deposited over the copper seed layer 416 again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum 421 is deposited to have a thickness of approximately a 50 Å. This can be achieved using a 3×10¹⁶ ion implant of aluminum normal to the wafer surface as shown by arrows 415. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum 421 is used to protect the copper seed layer 416 from oxidation prior to subsequent processing steps. The structure is now as appears in FIG. 4D.

[0073]FIG. 4E illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer 412 has served as a blocking layer to define the implant areas for the barrier/adhesion layer 414, the seed layer 416, and the layer of aluminum 421. The residual photoresist layer 412 is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer 412 includes removing the unwanted aluminum layer 421, the unwanted seed layer 416, and the unwanted barrier/adhesion layer 414 from other areas of the wafer's surface, e.g. from over a number of regions 413 outside of the trenches 410 on a top surface 419 of the first insulator layer 408. The structure is now as shown in FIG. 4E.

[0074] In FIG. 4F, a metallic conductor 420, or number of first level metal lines 420, is deposited over the seed layer 416 in the number of trenches 410. According to teachings of the metallic conductor 420, or number of first level metal lines 420, is selected from the group consisting of aluminum, copper, silver, and gold depending on the type of seed layer 416 which was deposited. According to this embodiment, a number of copper metal lines 420, or first level copper metal lines 420 are selectively formed on the copper seed layer 416. In one embodiment, the metallic conductor 420, or number of first level metal lines 420, is deposited using a selective CVD process. In another embodiment, depositing a metallic conductor 420, or number of first level metal lines 420, over the seed layer 416 includes depositing a metallic conductor 420 using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the number of trenches 410 to the top surface 419 of the first insulator layer 408.

[0075] As shown in FIG. 4G, the process sequence may be continued to form any number of subsequent metal layers in a multilayer wiring structure. FIG. 4G illustrates the structure after the next sequence of processing steps. In FIG. 4G, a dual damascene process is used to define and fill a first to a second level of vias and a second level metallurgy. To do so, a second polymer layer 424, or second layer of polyimide 424, is deposited over the wafer surface, e.g. the metallic conductor 420, or number of first level metal lines 420, and the first polymer layer 408. The second polymer layer 424 may similarly be deposited using, for example, the process and material described in co-pending and commonly assigned application U.S. Ser. No. 09/128,859, entitled “Copper Metallurgy in Integrated Circuits,” which is hereby incorporated by reference. In one embodiment, depositing a second polymer layer 424 includes depositing a foamed second polymer layer 424. In one embodiment, the second polymer layer 424 is deposited and cured, forming a 10,000 Å thick second polymer layer 424 after curing. As one of ordinary skill in the art will understand, upon reading this disclosure, other suitable thickness for the second polymer layer 424, or second insulator layer/material 424, may also be deposited as suited for forming a first to a second level of vias, e.g. second level vias, and a number of second level metal lines, the invention is not so limited. The second polymer layer 424, or second insulator layer/material 424 is patterned to define a second level of vias and a number of second level metal lines in the second insulator layer/material 424 opening to the metallic conductor 420, or number of first level metal lines 420. In other words, a second level of vias is defined in a second mask layer of photoresist 426 and then the second polymer layer 424 is etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of via openings 428 are defined in the polyimide. Using the dual damascene process, a number of second level metal lines are also defined in a second mask layer of photoresist 426 and the second polymer layer 424 is again etched, using any suitable process, e.g. reactive ion etching (RIE), such that a second level of metal line trenches 430 are defined in the polyimide. One of ordinary skill in the art will understand upon reading this disclosure, the manner in which a photoresist layer 426 can be mask, exposed, and developed using a dual damascene process to pattern a second level of via openings 428 and a second level of metal line trenches 430 in the second insulator layer/material 424.

[0076] As described previously, and according to the teachings of the present invention, a residual photoresist layer 426 is left in place on the second insulator layer/material 424 in a number of regions 432 outside of the second level of metal line trenches 430. A suitable plasma and/or wet cleaning process is used to remove any contaminates from the second level of via openings 428 and a second level of metal line trenches 430, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. The structure is now as appears in FIG. 4G.

[0077]FIG. 4H illustrates the structure after the next sequence of processing steps. In FIG. 4H, a second barrier/adhesion layer 434 is deposited in the second level of via openings 428 and a second level of metal line trenches 430 using a low energy ion implantation. As described above, in one embodiment according to the teachings of the present invention, depositing the second barrier/adhesion layer 434 includes depositing a layer of zirconium 434 having a thickness of approximately 5 to 100 Å. In alternate embodiments, depositing the second barrier/adhesion layer 434 includes depositing a barrier/adhesion layer 434 of titanium and/or hafnium. In one embodiment, depositing the layer of zirconium 434 includes depositing a layer of zirconium 434 having a thickness of approximately 15 Å. In one embodiment, this is achieved using a 10¹⁷ ion implant of zirconium. According to the teachings of the present invention, the layer of zirconium 434 is implanted at 100 electron volts (eV) into the surface of the second level of via openings 428 and a second level of metal line trenches 430 in the second polymer layer 424 using an implant angle normal to the wafer's surface as shown by arrows 425. The structure is now as appears in FIG. 4H.

[0078]FIG. 4I illustrates the structure after the next sequence of processing steps. In FIG. 4I, a second seed layer 436 is deposited on the second barrier/adhesion layer 434 using a low energy ion implantation. According to the broader teachings of the present invention, depositing the second seed layer 436 on the second barrier/adhesion layer 414 includes depositing a second seed layer 436 selected from the group consisting of aluminum, copper, silver, and gold. However, according to the teachings of the present embodiment, depositing the second seed layer 436 includes depositing a second layer of copper 436 having a thickness of approximately a 50 Å. In one embodiment, this is achieved using an 8×10¹⁶ ion implant of copper. According to the teachings of the present invention, using a low energy ion implantation includes implanting the layer of copper 436 at 100 electron volts (eV) into the second level of via openings 428 and the second level of metal line trenches 430 in the polymer layer. Also the layer of copper 436 is implanted at an angle normal to the wafer's surface as shown by arrows 437. As one of ordinary skill in the art will understand upon reading this disclosure, implanting the layer of copper 436 at an angle normal to the wafer's surface results in the second seed layer of copper 436 remaining on a bottom surface 438 in the second level of via openings 428 and to a much lesser extent on the side surfaces 440 of the second level of via openings 428 and a second level of metal line trenches 430. In one embodiment, an optional layer of aluminum 441 is deposited over the second copper seed layer 436 again using a low energy ion implantation of 100 electron volts (eV). The optional layer of aluminum is deposited to have a thickness of approximately a 50 Å. In one embodiment, this is achieved using a 3×10¹⁶ ion implant of aluminum normal to the wafer surface. As one of ordinary skill in the art will understand upon reading this disclosure, the layer of aluminum 441 is used to protect the second copper seed layer 436 from oxidation prior to subsequent processing steps. The structure is now as appears in FIG. 4I.

[0079]FIG. 4J illustrates the structure after the next sequence of processing steps. As one of ordinary skill in the art will understand upon reading this disclosure, the residual photoresist layer 426 has served as a blocking layer to define the implant areas for the second barrier/adhesion layer 434, the second seed layer 436, and the aluminum layer 441. The residual photoresist layer 426 is now removed using a wet strip process, as the same will be understood by one of ordinary skill in the art upon reading this disclosure. According to the teachings of the present invention, removing the residual photoresist layer 426 includes removing the unwanted aluminum layer 441, the unwanted seed layer 436, and the unwanted barrier/adhesion layer 434 from other areas of the wafer's surface, e.g. from over a number of regions 432 outside of second level of metal line trenches 430 on a top surface 442 of the second insulator layer 424. The structure is now as shown in FIG. 4J.

[0080] In FIG. 4K, a second metallic conductor 444, or second core conductor 444, is deposited over or formed on the second seed layer 436 and within the second barrier/adhesion layer 434 in the second level of via openings 428 and the second level of metal line trenches 430 in the polymer layer. In this embodiment the second metallic conductor 444, or second core conductor 444, is copper, but in other embodiments of the present invention the second metallic conductor 444, or second core conductor 444, can be selected from the group consisting of aluminum, silver, and gold. In one embodiment, the second metallic conductor 444, or second core conductor 444, is deposited using a selective CVD process. In another embodiment, depositing a second metallic conductor 444, or second core conductor 444, over on the second seed layer 436 and within the second barrier/adhesion layer 434 includes depositing a second metallic conductor 444, or second core conductor 444, using electroless plating. Electroless copper plating is used to deposit sufficient copper to fill the second level of via openings 428 and the second level of metal line trenches 430 to the top surface 442 of the second insulator layer 424. Thus, the second barrier/adhesion layer 434, the second seed layer 436, and the second metallic conductor 444, or second core conductor 444, constitute a second number of conductive structures which includes a number of second level vias and a number of second level metal lines which are formed over and connect to a first number of conductive structures, e.g. the metallic conductor 420, or number of first level metal lines 420.

[0081] As one of ordinary skill in the art will understand upon reading this disclosure, the above described method embodiments can be repeated until the requisite number of metal layers are formed.

[0082]FIG. 4L illustrates the structure following the final sequence of processing steps. Upon completion of the last level of metal, the entire polymer structure, e.g. first polymer layer 408 and second polymer layer 424, are removed using an O₂ plasma etch. The structure is now as appears in FIG. 4L.

[0083]FIG. 5, is an illustration of an embodiment of an integrated circuit formed according to the teachings of the present invention. As shown in FIG. 5, the integrated circuit includes a metal layer in an integrated circuit. The metal layer FIG. 5, is an illustration of an embodiment of an integrated circuit 503 formed according to the teachings of the present invention. As shown in FIG. 5, the integrated circuit 503 includes a metal layer in an integrated circuit. The metal layer includes a number of first level vias 507A and 507B connecting to a number of silicon devices 501A and 501B in a substrate 500. A number of first level metal lines 520 are formed above and connect to the number of first level vias 507A and 507B. A barrier/adhesion layer 514 having a thickness in the range of 5 to 150 Angstroms is formed on the number of first level vias 507A and 507B. A seed layer 516 having a thickness in the range of 5 to 150 Angstroms is formed at least between a portion of the barrier/adhesion layer 514 and the number of first level metal lines 520. As described above the barrier adhesion layer 514 having a thickness in the range of 5 to 150 Angstroms includes a barrier/adhesion layer selected from the group consisting of titanium, zirconium, and hafnium. In one embodiment, as shown in FIG. 5, the number of first level vias 507A and 507B connecting to a number of silicon devices 501A and 501B in substrate 500 are surrounded by an insulator layer 502.

[0084] As described above the number of first level metal lines is selected from the group consisting of Aluminum, Copper, Silver, and Gold. In one embodiment, the integrated circuit 503 comprises a portion of an integrated memory circuit 503. In this embodiment, the number of silicon devices 501A and 501B includes one or more transistors 501A and 501B in the substrate 500.

[0085] As one of ordinary skill in the art will understand upon reading this disclosure, any one of the embodiments as shown in FIGS. 1K, 2K, 3K, and/or 4L can comprise a portion of an integrated circuit according to the teachings of the present invention.

[0086]FIG. 6 illustrates an embodiment of a system 600 including a portion of an integrated circuit formed according to any of the embodiments described in the present application. As one of ordinary skill in the art will understand upon reading this disclosure, this system 600 includes a processor 610 and an integrated circuit, or integrated memory circuit 630 coupled to the processor 610. The processor 610 can be coupled to the integrated memory circuit 630 via any suitable bus, as the same are known and understood by one of ordinary skill in the art. In the embodiment, the processor 610 and integrated circuit 630 are located on a single wafer or die. Again, at least a portion of the integrated circuit 630 includes a portion of an integrated circuit 603 as disclosed in the various embodiments provided herein.

CONCLUSION

[0087] Thus, structures and methods have been provided which improve the performance of integrated circuits according to shrinking design rules. The structures and methods include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. According to the teachings of the present invention, the selective deposition of the metal lines avoids the need for multiple chemical mechanical planarization (CMP) steps. The low energy ion implantation of the present invention allows for the distinct placement of both the diffusion barrier and the seed layer. A residual resist can be used to remove the diffusion barrier and the seed layer from unwanted areas on a wafer surface. The structures formed by the described novel processes accommodate aluminum, copper, gold, and silver metal interconnects.

[0088] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. 

What is claimed:
 1. An integrated circuit comprising: a substrate including one or more devices; a first insulating layer overlying the substrate having one or more first level vias connecting to the one or more devices in the substrate; and a second insulating layer overlying the first insulating layer, the second insulating layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including: a first level metal line; a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias; and a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
 2. The integrated circuit of claim 1, wherein the second insulating layer includes a foamed polymer layer.
 3. The integrated circuit of claim 1, wherein the second insulating layer includes a foamed polyimide layer.
 4. The integrated circuit of claim 2, wherein first insulating layer includes a Si₃N₄ layer having a thickness between about 100 Angstroms to about 500 Angstroms.
 5. The integrated circuit of claim 1, wherein the barrier/adhesion layer includes one or more of titanium, zirconium, and hafnium.
 6. The integrated circuit of claim 1, wherein the seed layer includes copper and the first level metal line includes a copper metal line.
 7. The integrated circuit of claim 1, wherein the integrated circuit is a memory device.
 8. An integrated circuit comprising: a substrate including one or more devices; an insulator layer overlying the substrate, the insulator layer having one or more first level vias connecting to the one or more devices in the substrate; and a polymer layer overlying the insulator layer, the polyimide layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including: a first level metal line; a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias; and a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
 9. The integrated circuit of claim 8, wherein the polymer layer includes a polyimide layer.
 10. The integrated circuit of claim 8, wherein the insulator layer includes Si₃N₄ having a thickness between about 100 Angstroms to about 500 Angstroms.
 11. The integrated circuit of claim 8, wherein the barrier/adhesion layer includes one or more of titanium, zirconium, and hafnium.
 12. The integrated circuit of claim 8, wherein the seed layer includes copper.
 13. The integrated circuit of claim 8, wherein the integrated circuit is a memory device.
 14. An integrated circuit comprising: a substrate including one or more devices; an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and an oxide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including: a layer of titanium or zirconium having a thickness of approximately 50 Angstroms disposed on a first level via of the number of first level vias; a first layer of aluminum on the layer of titanium or zirconium having a thickness of approximately 50 Angstroms; a layer of copper on the first layer of aluminum having a thickness of approximately 10 Angstroms; and a second layer of aluminum on the layer of copper having a thickness of approximately 50 Angstroms.
 15. The integrated circuit of claim 14, wherein the insulator layer includes Si3N4 having a thickness between about 100 Angstroms to about 500 Angstroms.
 16. The integrated circuit of claim 14, wherein the oxide layer includes a fluorinated silicon oxide layer.
 17. The integrated circuit of claim 14, wherein the integrated circuit is a memory device.
 18. An integrated circuit comprising: a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; and a first number of conductive structures formed over and connecting to the number of first level vias in the first insulator layer, each conductive structure, each conductive structure of the first number of conductive structures including: a layer of zirconium having a thickness of approximately 15 Angstroms disposed on a first level via of the number of first level vias; a seed layer of copper on the layer of zirconium having a thickness of approximately 50 Angstroms; and a copper metal line formed on the seed layer of copper; and a polymer layer surrounding the first number of conductive structures.
 19. The integrated circuit of claim 18, wherein each conductive structure further includes a layer of aluminum having a thickness of approximately 50 Angstroms formed between the seed layer of copper and the copper metal line.
 20. The integrated circuit of claim 18, wherein the polymer layer includes a foamed polymer layer.
 21. The integrated circuit of claim 18, wherein the integrated circuit further includes: a second number of conductive structures including a number of second level vias and a number of second level metal lines formed above and connecting to the first number of conductive structures, wherein each of the second number of conductive structures includes: a layer of zirconium having a thickness of approximately 15 Angstroms; a seed layer of copper on at least a portion of the layer of zirconium having a thickness of approximately 50 Angstroms; and a core copper conductor over the seed layer and within the layer of zirconium.
 22. The integrated circuit of claim 18, wherein the integrated circuit is a memory device.
 23. An integrated circuit comprising: a number of first level vias in a first insulator layer connecting to a number of silicon devices in a substrate; a first number of conductive structures formed over and connecting to the number of first level vias in the first insulator layer, each conductive structure, comprising: a first barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms disposed on a first level via of the number of first level vias; a first seed layer formed on at least a portion of the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms; and a first core conductor formed on the first seed layer; a polymer surrounding the first number of conductive structures; and a second number of conductive structures include a number of second level vias and a number of second level metal lines, wherein the second number of conductive structures are formed over and connect to the first number of conductive structures, and wherein each of the second number of conductive structures includes: a second barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms; a second seed layer formed on at least a portion of the barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms; and a second core conductor formed on the second seed layer.
 24. The integrated circuit of claim 23, wherein the second number of conductors is surrounded by a polyimide layer.
 25. The integrated circuit of claim 24, wherein the polyimide layer includes a foamed polyimide layer.
 26. The integrated circuit of claim 23, wherein the first and the second barrier/adhesion layers include one or more of tantalum nitride, titanium, zirconium, and hafnium.
 27. The integrated circuit of claim 23, wherein the first and the second core conductors include a metal conductor having one or more of aluminum, copper, silver, and gold.
 28. The integrated circuit of claim 23, wherein the first and the second seed layers include one or more of aluminum, copper, silver, and gold.
 29. The integrated circuit of claim 18, wherein the integrated circuit is a memory device.
 30. An integrated circuit comprising: a number of first level vias in a first insulator layer connecting to a number of transistors in a substrate; and an oxide layer formed over the number of first level vias in the first insulator layer, wherein the oxide layer includes a number of conductive structures connecting from a top surface of the oxide layer to the number of first level vias, each conductive structure comprising: a layer of tantalum nitride having a thickness of approximately 5 to 100 Angstroms disposed on a first level via of the number of first level vias; a seed layer of copper on the layer of tantalum nitride having a thickness of approximately 100 Angstroms; and a copper metal line formed on the seed layer of copper.
 31. The integrated circuit of claim 30, wherein each conductive structure further includes a layer of tantalum nitride forming a top surface of each conductive structure such that the top surface of each conductive structure is level with the top surface of the oxide layer.
 32. The integrated circuit of claim 30, wherein the oxide layer includes a fluorinated silicon oxide layer.
 33. The integrated circuit of claim 30, wherein at least one of the number of first level vias is filled with tungsten.
 34. The integrated circuit of claim 30, wherein at least one of the number of first level vias is within a titanium silicide liner.
 35. The integrated circuit of claim 30, wherein the integrated circuit is a memory device.
 36. An integrated circuit comprising: a first level via in a first insulator layer connecting to a transistor in a substrate; and an oxide layer formed over the first level via in the first insulator layer, wherein the oxide layer includes a conductive structure connecting from a top surface of the oxide layer to the first level via, the conductive structure including: a barrier/adhesion layer having two material layers, the barrier/adhesion layer disposed on a first level via of the number of first level vias; a seed layer on the barrier/adhesion layer; a layer of aluminum on the seed layer, the layer of aluminum having a thickness of about 50 Angstroms; and a metal line formed on the layer of aluminum.
 37. The integrated circuit of claim 36, wherein the barrier/adhesion layer has a thickness of approximately 5 to 100 Angstroms.
 38. The integrated circuit of claim 36, wherein the barrier/adhesion layer includes one or more of titanium, zirconium, and hafnium.
 39. The integrated circuit of claim 36, wherein the seed layer includes one or more of silver and gold.
 40. The integrated circuit of claim 36, wherein the first level via is a tungsten via and is contained in a liner.
 41. The integrated circuit of claim 36, wherein the first level via is contained in a liner that separates the first level via from a layer of Si₃N₄.
 42. The integrated circuit of claim 36, wherein the seed layer has a thickness of approximately 10 Angstroms.
 43. The integrated circuit of claim 36, wherein the integrated circuit is a memory device.
 44. An integrated circuit comprising: a first level via in a first insulator layer connecting to a transistor in a substrate; a titanium silicide liner that contains the first level via; a conductive structure formed over the first level via in the first insulator layer, the conductive structure including: a barrier/adhesion layer disposed on the first level via; a seed layer on the barrier/adhesion layer; and a metal line disposed above the seed layer; and a second insulator layer containing the conductive structure.
 45. The integrated circuit of claim 44, wherein the barrier/adhesion layer has a thickness in the range of 5 to 150 Angstroms.
 46. The integrated circuit of claim 44, wherein the barrier/adhesion layer includes CuTi.
 47. The integrated circuit of claim 44, further including a layer of aluminum between the seed layer and the metal line.
 48. The integrated circuit of claim 44, wherein the second insulator layer includes a fluorinated silicon oxide layer.
 49. The integrated circuit of claim 44, wherein the integrated circuit is a memory device.
 50. An integrated circuit comprising: a first level via in a first insulator layer connecting to a transistor in a substrate; a first conductive structure formed over the first level via in the first insulator layer, the first conductive structure including: a first barrier/adhesion layer disposed on the first level via; a first seed layer disposed on the first barrier/adhesion layer; and a first metal line disposed above the first seed layer; a second insulator layer containing the first conductive structure; a second conductive structure having a portion disposed on the first metal line of the first conductive structure, the second conductive structure including: a second barrier/adhesion layer disposed on the first metal line; a second seed layer disposed on the second barrier/adhesion layer; and a second metal line disposed above the second seed layer.
 51. The integrated circuit of claim 50, further including a layer of aluminum between the first seed layer and the first metal line.
 52. The integrated circuit of claim 50, further including a layer of aluminum between the second seed layer and the second metal line.
 53. The integrated circuit of claim 50, wherein the first metal line and the second metal line are composed of different materials.
 54. The integrated circuit of claim 50, wherein the first metal line and the second metal line each include one or more of copper, aluminum, silver, and gold.
 55. The integrated circuit of claim 50, wherein the first and the second seed layers include one or more of aluminum, copper, silver, and gold.
 56. The integrated circuit of claim 50, wherein the first and the second barrier/adhesion layers each have a thickness in the range of 5 to 150 Angstroms.
 57. The integrated circuit of claim 50, wherein the first and second barrier/adhesion layers each include one or more of titanium, zirconium, and hafnium.
 58. The integrated circuit of claim 50, wherein the integrated circuit is a memory device.
 59. An integrated circuit, comprising: a first level via in a first insulator layer connecting to a silicon device in a substrate; a liner containing the first level via; a first conductive structure formed over the first level via in the first insulator layer, the first conductive structure including: a first barrier/adhesion layer disposed on the first level via; a first seed layer disposed on the first barrier/adhesion layer; and a first metal line disposed above the first seed layer; a second insulator layer containing the first conductive structure; a second conductive structure having a portion disposed on the first metal line of the first conductive structure, the second conductive structure including: a second barrier/adhesion layer disposed on the first metal line; a second seed layer disposed on the second barrier/adhesion layer; and a second metal line disposed above the second seed layer.
 60. The integrated circuit of claim 59, wherein the liner contains titanium silicide.
 61. The integrated circuit of claim 59, wherein the liner separates the via from a layer of Si₃N₄.
 62. The integrated circuit of claim 59, wherein the first metal line and the second metal line each include one or more of copper, aluminum, silver, and gold.
 63. The integrated circuit of claim 59, wherein the first and second barrier/adhesion layers each have a thickness in the range of 5 to 150 Angstroms.
 64. The integrated circuit of claim 59, wherein the first and second barrier/adhesion layers each include one or more of titanium, zirconium, and hafnium.
 65. The integrated circuit of claim 59, wherein the integrated circuit is a memory device.
 66. A system, comprising: a processor; and an integrated circuit coupled to the processor, wherein the integrated circuit includes: a substrate including one or more devices; a first insulating layer overlying the substrate having one or more first level vias connecting to the one or more devices in the substrate; and a second insulating layer overlying the first insulating layer, the second insulating layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including: a first level metal line; a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias; and a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
 67. The system of claim 66, wherein the second insulating layer includes a polymer layer.
 68. The system of claim 66, wherein the second insulating layer includes a foamed polymer layer.
 69. The system of claim 66, wherein the barrier/adhesion layer includes one or more of titanium, zirconium, and hafnium.
 70. The system of claim 66, wherein the seed layer includes copper and the first level metal line includes a copper metal line.
 71. The system of claim 66, wherein the integrated circuit is a memory device.
 72. A system, comprising: a processor; and an integrated circuit coupled to the processor, wherein the integrated circuit includes: a substrate including one or more transistors; an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and a polyimide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including: a first level metal line; a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias; and a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
 73. The system of claim 72, wherein the barrier/adhesion layer includes one or more of titanium, zirconium, and hafnium.
 74. The system of claim 72, wherein the seed layer includes copper and the first level metal lines includes a copper metal line.
 75. The system of claim 72, wherein the integrated circuit is a memory device.
 76. A system, comprising: a processor; and an integrated circuit coupled to the processor, wherein the integrated circuit includes: a substrate including one or more transistors; an insulator layer overlying the substrate having one or more first level vias connecting to the one or more transistors in the substrate; and an oxide layer overlying the insulator layer including one or more conductive structures formed above and connecting to the one or more first level vias, each of the one or more conductive structures including: a first level metal line; a barrier/adhesion layer having a thickness in the range of 5 to 150 Angstroms formed on the number of first level vias; and a seed layer having a thickness in the range of 5 to 150 Angstroms formed at least between a portion of the barrier/adhesion layer and the first level metal line.
 77. The system of claim 76, wherein the barrier/adhesion layer includes one or more of titanium, zirconium, and hafnium.
 78. The system of claim 76, wherein the seed layer includes copper and the first level metal lines includes a copper metal line.
 79. The system of claim 76, wherein the integrated circuit is a memory device. 